Hello. We are experiencing an issue that seems to require more expertise, i.e., internal knowledge of the product.
The problem is:
Kflop generates inconsistent pulse widths between different channels despite both channels running the same code with the same parameters. On one channel the width of the low pulses is less than a uSEC and does not vary in rate. The FPGA(STEP_PULSE_LENGTH_ADD) command is not having any effect.

We have debugged as much as we can with the knowledge of the product we have and need a consultant. I have been trying to get a list of consultants from Dynomotion but their communication portals seem to be all AI and end up in a chat loop leading nowhere.
Anyway, looking for technical expertise.