FPGA cannot be loaded normally after connecting to GPIO

The FPGA board currently designed uses the FPGA model XC7Z100-FFG900. Recently, there was a problem during joint debugging with the customer. The FPGA has several GPIOs that are linked to the customer’s board through the connector. The corresponding pin on the customer's board is in the 3.3V high level state for a long time. After connecting to the GPIO of our single board, our FPGA cannot be loaded normally. The GPIO pins are directly connected from the FPGA to the inter-board connector, and the connector is disconnected to return to normal. After testing, it is found that due to the high level of the opposite end of the GPIO link, the voltage of our GPIO corresponding to BANK's VCCO33 is pulled up to about 2.1V. In theory, the INPUT pin of the FPGA is in a high impedance state at this time. I don't know why this happens. In this scenario, I found a few boards and tried them later, and this problem still exists.
Please refer to the schematic diagram. In fact, the GPIO is directly pulled from the FPGA to the inter-board connector, and there is no other link.