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  1. #1
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    6amp 60v 10 microstep bipolar drive

    After a 3 year absence, I finally got around to building a drive based on the information presented by Mariss in the "5 Microstep drive CPLD tutorial" threads. The circuit is essentially the one presented at the end of that document. I added the JTAG programming port and the voltage regulators. The board is double sided, made by toner transfer, with .05" vias and 12 mil traces. The layout is very roughly based on the Geckodrive G251. As it turned out, this is not suitable for my toner transfer board because the unevenness and the lack of through hole plating made it impossible to clamp the fets down. I will try a different fet layout on the next iteration.

    The verilog code is the one posted by Pminmo. I made changes to support 10 instead of 5 microsteps. I am currently testing it on a Keling kl23h276-30-8b nema 23, 280 oz-in, 4 amp stepper.

    Driving it with 33v and 2 amps, I am able to reach 1800 rpm unloaded, which is the maximum limits of the demo version of Mach 3. I applied a very simple mechanical resonance damper to prevent the motor from stalling.

    It is still work in progress. Because I don't have a ground plane, it is difficult to avoid parasitic inductances which resulted in periodic oscillations from the mosfets. I was able to stop them by using gate resistors, but seems to cause severe shoot through. I am experimenting with different solutions. I will probably need to redo the power section.
    Attached Thumbnails Attached Thumbnails stepper_bd.jpg  

  2. #2
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    Quote Originally Posted by H500 View Post
    After a 3 year absence, I finally got around to building a drive based on the information presented by Mariss in the "5 Microstep drive CPLD tutorial" threads. The circuit is essentially the one presented at the end of that document.
    My search for a "5 Microstep drive CPLD tutorial" document brought up a PDF that does not contain such a circuit diagram. Maybe I need to work on my search skills, but could you post a link to the circuit diagram that you are using?

  3. #3
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    Quote Originally Posted by doorknob View Post
    My search for a "5 Microstep drive CPLD tutorial" document brought up a PDF that does not contain such a circuit diagram. Maybe I need to work on my search skills, but could you post a link to the circuit diagram that you are using?
    The full pdf file is located in the "cpld tutorial" thread, posting 116. Be sure to get the corrected code from posting 183.

    At least 2 others have photo evidence of their project, but I did not see any writeup on a fully working one yet. I'm surprised that there hasn't been more activity with this design. In my opinion, it is one of, if not the most capable open source stepper drive presented on the web. The project require more development before it's ready, but it's a great leaning tool for learning verilog and mosfet power design.

  4. #4
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    Here's a shot of the resonance damper that I've been playing with. It's simply a gear from the mini-lathe. I had an assortment to pick from. The one in the photo is about 2" in diameter. The gear fits loosely on the shaft. The key slot is slightly oversized relative to the key. The disc (gear) normally rotates with the shaft. But when resonance occur, the key rattle against the slot. This dissipates the energy and dampens the oscillation.

    It worked very well.
    Attached Thumbnails Attached Thumbnails damper.jpg  

  5. #5
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    Thanks for the pointer to the info.

    I'm not quite ready to learn about CPLD programming, but I would like to know more about working with power MOSFETs, and figured that this might be a useful source...

  6. #6
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    Quote Originally Posted by H500 View Post
    The full pdf file is located in the "cpld tutorial" thread, posting 116. Be sure to get the corrected code from posting 183.
    In the interests of saving your time and not overloading the cnczone search engine, here are direct links to those two posts... and the thread (via the thread link in the upper right corner of either of these)

    http://www.cnczone.com/forums/632482-post116.html

    http://www.cnczone.com/forums/660885-post183.html



  7. #7
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    Quote Originally Posted by H500 View Post
    I'm surprised that there hasn't been more activity with this design. In my opinion, it is one of, if not the most capable open source stepper drive presented on the web. The project require more development before it's ready, but it's a great leaning tool for learning verilog and mosfet power design.
    It does look really interesting... what specific further development is needed at this point?

  8. #8
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    Quote Originally Posted by James Newton View Post
    It does look really interesting... what specific further development is needed at this point?
    There are several items that need work

    1. EMI. There's more ringing in the waveform than I would like. It manifest as snow on a weak TV channel.

    2. I had to disable the fast decay mode. When enabled, the pwm freq becomes 10khz instead of 20. I think it's caused by shoot through or ringing, causing the winding to need 2 cycles to reach the set point.

    Athough the slow decay waveform does not good on the scope, I actually think it works pretty well. But I don't have anything to compare to. Perhaps the vibration damper would not rattle as much if the waveform stayed sinusoidal at higher frequencies.

    3. The drive has a very soft hiss at one of the microstep postion. This is minor, but I like to see if I can eliminate it.

    I think all the issues are related to the layout of the power section. I think I will try grafting on other layouts to see what works best.

  9. #9
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    I added gate resistors to each of the upper mosfets. This eliminated the 1Mhz oscillations that produced the intermittent hissing noise.

    The big issue remaining is why the PWM frequency falls to 10 Khz when the fast decay mode is enabled. The attached trace shows the waveform across the current sensing resistor. Vertical scale is 1 amp/div. Timebase is 50uS/div.

    I suspect that it's due to the lack of slope compensation when the motor is stepping. The PWM duty cycle appears to be alternating between zero and 100%.
    Attached Thumbnails Attached Thumbnails fast_decay.jpg  

  10. #10
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    I added slope compensation during stepping. That corrected the PWM frequency problem.

    The fast decay mode actually seems to vibrate more than the recirculating one. I noticed no improvement in performance. However, I notice a glitch at the 0 and 90 degree sine positions. .

    The cause is a mystery at this point.
    Attached Thumbnails Attached Thumbnails fast decay.jpg  

  11. #11
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    On a more general level: Is there a real point to learning / using CPLD's these days given the availability of very low cost, very fast microcontrollers? It would seem like most of what you are doing could be accomplished in uC firmware using C or ASM without having to learn an HDL like verilog / VHDL. Or is there some advantage that the CPLD brings that a uC can't possibly provide?

  12. #12
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    The key is to use the proper tool for the job. Both has strengths and weaknesses.

    Technically, you could do everything with a micro, but even a fast mcu is much slower since the code is executed sequentially. Verilog code translate into hardware connections inside the cpld which runs in parallel. A simple example would be the pwm sine wave code. On a mcu without PWM, much of your cpu cycles would be used up. You would need to worry about responding to other events fast enough to avoid jitter. With a cpld, your primary concern is running out of gates to connect. Speed is not an issue when doing motor controllers.

    Learning verilog is no harder than learning another assembly language. You only need to learn a small subset in order to do a lot. I'm a pure novice at this point.

    The biggest limitation of cplds is that you have very limited resources to work with when compared to a mcu. This make experimentation more difficult. My next project will involve using a DSP to do the same thing. The ones designed for motor control have so much goodies on board. I like to see how well they work.

  13. #13
    An MCU is a sequential machine while a CPLD or FPGA is a parallel machine.

    Mariss

  14. #14
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    I understand all that, but the posts above discuss PWM at 10kHz thereabouts.

    Even with a low-end microcontroller they often come with TWO inbuilt hardware PWM modules that will do 50kHz or 100kHz pwm.

    So I think I'm asking the same thing as James, why would you need a CPLD to generate 2 signals at 10kHz PWM? This would be fairly trivial to do with just about any micro.

    Or is there some performance benefit to using the CPLD for this project that would not occur when using a micro?

  15. #15
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    The main advantages are speed, cost and ease of routing the pcb. For this application, from a hobbyist perspective, only the last item matters.

    In fact, I think that a DSP would probably provide greater opportunity for experimenting with fancy control techniques such as phase compensation and positional feedback without having to use the soldering iron. But I don't see CPLDs as a replacement for micros. A cpld can replace all the glue logic in a .5" x .5" package that will likely cost less than the discrete parts.

  16. #16
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    I am noticing a small amount of resonance (vibration) at one or two frequencies. It's enough to make the motor noisier, but not enough to result in missing steps. I wonder if it is the drive or if the motors themselves lack linearity. I suspect the latter, since I see the same behavior with all the drives I used so far.

    If anyone is using the same Keling stepper with another drive, I would be interested to know if you have any resonance.

  17. #17
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    Here is the schematic and CPLD programming file. I have tested the the design with 34v and 6 amps, which is the limits of my current power supply. In addition to the HV supply a small 12vdc supply is needed to drive the fet gates and the logic circuit.

    The tb6560 appears to be the design of choice, but it's quite anemic since it can only take about 30v. A discrete design like this will potentially deliver double the speed at about the same cost.
    Attached Files Attached Files

  18. #18
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    I've followed this thread and the original one and find it very strange that there is not much animo.

    The TB6560 is useable but limited in supply and current, this design allows for higher volts and amps. The only reason why I didn't use it before is that CPLD thingy and it's programming, I just don't understand it but have experience with several kinds of microcontrollers. I know that I could learn it but am getting old and have no time enough.

    When looking at the problems you encountered and solutions: can we conclude the following:

    1: The drive is performing like other "normal" ones but not like Gecko's or others with resonance suppression.

    2: The reason for the needed gate resistors is probably due to your PCB design as you already stated. some other strange effects might also be caused by this?

    Question: You added slope compenstation to correct the PWM frequency problem. I thought this was already present in the original implementation or did I miss something?

    I am now very tempted to design a PCB (but through hole: old eyes) because:
    - your "firmware" support 10 microsteps.
    - also found a simple parrallel port programmer.

    The only thing I still have to check is the CPLD development and hardware programming software. If this is cheap then I might have a go at it.

    Thanks for your effort and regards,
    Luc.

  19. #19
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    Quote Originally Posted by lucas View Post
    The only reason why I didn't use it before is that CPLD thingy and it's programming, I just don't understand it but have experience with several kinds of microcontrollers. I know that I could learn it but am getting old and have no time enough.
    I don't really understand verilog yet. But I was able to change code without difficulty using the excellent documentation provided by Mariss. If you used the behavioral approach instead, then the code looks a lot like C.
    1: The drive is performing like other "normal" ones but not like Gecko's or others with resonance suppression.
    Yes. There is no mid-band resonance suppression. You will need to use a flywheel damper if you want to drive the motor to full speed.
    2: The reason for the needed gate resistors is probably due to your PCB design as you already stated. some other strange effects might also be caused by this?
    Yes. An ideal routing is harder to accomplish when using only a 2 layer route. The parasitic inductance in the gate caused oscillations. The gate resistors eliminated them. You might be able to leave them out if your board does not oscillate.
    Question: You added slope compenstation to correct the PWM frequency problem. I thought this was already present in the original implementation or did I miss something?
    The original code only had compensation during standby. I believe it was a mistake. The PWM is not stable without it. I would recommend using a 1M pot so that the amount of compensation could be fine tuned for the motor you are using.

    I am now very tempted to design a PCB (but through hole: old eyes) because:
    - your "firmware" support 10 microsteps.
    - also found a simple parrallel port programmer.
    The drive is very smooth except at the resonant points. I believe the low freq resonance is caused by the motor non-linearity.

    Do a search for the parallel cable 3 circuit. It's just a few gates an some passive components. But I'm not sure if the Xilinx programmer software still support it. It only mentions parallel cable IV.

    The only thing I still have to check is the CPLD development and hardware programming software. If this is cheap then I might have a go at it.
    The Xilinx software can be downloaded for free.

  20. #20
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    Something I would really like to add is mid band resonance compensation. I believe this can be done by adding a phase lead to the motor current. I'm not sure how to do this with the cpld, but according to Microchip, a PI current controller with anti-windup will achieve this. The only catch is that a DSP would be required. On advantage of this approach is that there is no need to change the hardware when changing control techniques.

    I am reviewing several possibilities. Some of these chips contain everything you need for a controller other than the power section! This will be my next project.

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