[Mariss Freimanis]

Thanks Mariss,

It appears that there used to be a post on the xilinx site showing how to construct an oscillator but it appears that they have removed it. There are still links to such a post but the go to a 404 error.

As usual you seem to be the man with the answers.

Thanks again,
Alan

Alan,

The way I use CPLDs is a little different than the way they are intended to be used. An XC2C32A CPLD can run with a 50MHz to 100MHz clock. It is intended to be a replacement for fast 'glue' logic and many if not most applications utilize this kind of speed.

Designing a microstep drive or a servodrive doesn't require and cannot use anywhere near that kind of clock speed. 5MHz or less is plenty and clock frequency accuracy is of little consequence. We get +/-5% over temperature and supply voltage tolerances. That is why an RC Schmidt inverter oscillator is more than adequate.

I chose the CoolRunner II for characteristics that are vital to me. Foremost is zero DC supply current. Its supply current is a linear function of clock frequency and at 5MHz it's not much (100uA or less). Other CPLDs draw 100mA or more and that is a deal-breaker in my applications. Second, the CoolRunner II has 'true' CMOS inputs. They can be set to 'float' and 'Schmidt' which makes them ideal for quasi-analog inputs. Also the device and its development system is intuitive to use and free of vices.

Finally, it turns out 32 and 64 macrocells are sufficient (barely, but just sufficient) to squeeze out fairly sophisticated designs. The QFN package (QFN32 and QFN48) accommodates only the 32 and 64 macrocell parts. The 128, 256 and larger macrocell parts come in enormous VQFP-100 and VQFP-144 or BGA packages. I cannot use such large parts owing to product size constraints and I'm unwilling to use BGA because of the package expense and the inability to visually inspect solder connections.

Mariss

[pminmo]

I started with the Digilent C-mod ( http://www.digilentinc.com/Products/...=419&Prod=CMOD) and their parallel JTAG Programming Cable. Works pretty well with ISE although sometimes it can be a bit contrary to get the JTAG chain initialized, but I'm sure it's more of an ISE issue than Digilent. Once I progress to my own boards then the C-Mod sits..... But I would recommend it as a cheap way to get started with Coolrunner parts and CPLD's.

[JonLed]

I thought links to these two threads would be appropriate, since one discusses which Coolrunner kit to buy.

http://www.cnczone.com/forums/showthread.php?t=74497

http://www.cnczone.com/forums/showthread.php?t=80541

Mine should be here tomorrow.

Jon

[Mariss Freimanis]

I pounded out the first chapter and I'm half-way through chapter 2. Chapter 2 really gets down to business.:-) Let me know what you think.

Mariss

[pminmo]

I think your doing a great job! I wish I had this a year ago......

[Bubba]

Mariss,
Well written and I went right though it (except for FAT finger typing) and was able to complete this chapter with little problem.

I downloaded V11/1 before I saw your post to use 10.x, but so far there seems to be no real difference.

I do have one question however and maybe this is a difference. You talk about assigning pins and in V11.1, I had to input the physical pin numbers. I followed yours, but did YOU assign the pin numbers or was that done by the software?

[pminmo]

Heres some code that I have used below for quarterstep. I'm real interested in Mariss's pwm code as this seems to be inefficient:

/// Quarter step translator /////
module QTranslator (clk, step, reset, dir, q );

input clk, reset, step, dir;
output [17:0] q;
reg [3:0] tmp;
reg [17:0] q;

always @(posedge step or posedge reset)
begin
if (reset)
tmp = 4'b0000;
else
if (dir)
tmp = tmp + 1;
else
tmp = tmp - 1;
end
// phases-pwma-pwmb
// q abcd-xxxxxxx-xxxxxxx
always @(posedge clk)
begin
case (tmp)
4'h0: q <= 18'b001000000001111111; //0
4'h1: q <= 18'b101001100011110101; //22.5
4'h2: q <= 18'b101010110101011010; //45
4'h3: q <= 18'b101011101010110001; //67.5
4'h4: q <= 18'b100011111110000000; //90
4'h5: q <= 18'b100111101010110001; //102.5
4'h6: q <= 18'b100110110101011010; //135
4'h7: q <= 18'b100101100011110101; //157.5
4'h8: q <= 18'b000100000001111111; //180
4'h9: q <= 18'b010101100011110101; //202.5
4'hA: q <= 18'b010110110101011010; //225
4'hB: q <= 18'b010111101010110001; //247.5
4'hC: q <= 18'b010011111110000000; //270
4'hD: q <= 18'b011011101010110001; //292.5
4'hE: q <= 18'b011010110101011010; //315
4'hF: q <= 18'b011001100011110101; //337.5
endcase
end

endmodule

/// PWM code ////

module PWM (DC, CLK ,Q , RESET);
input [6:0] DC; // duty cycle input
input CLK;
input RESET;
output Q;
reg [7:0] acc; // accumulator has one more bit than the duty cycle
assign Q=acc[7]; // output is the 8th bit
initial acc=0; // for simulation only
always @(posedge CLK)
begin
if (RESET) acc=0;
acc=acc[6:0]+DC; // only add with 8 bits.
end
endmodule

[Mariss Freimanis]

Bubba,

I did the PACE section to show how pins are assigned. The most important part there was to make sure:

Slew = SLOW
I/O Std. = LVCMOS33
Termination = FLOAT
Schmitt = ON

That required a screen capture for the picture so pin numbers were filled in as well to make it all look realistic. I do this step only after the entire project's code compiles without warnings and errors. Until then, I'm prone to adding, renaming and removing input and output declarations as the project progresses.

I like to implement the design every time a new section gets done. This way I catch errors on each new section. It avoids a massive heart attack from seeing 3,000 error messages if the first implementation comes after the entire project is written.

Mariss

[Bubba]

Mariss,
Thanks for the explanation, figured that is what was happening, but as they say no question, no answer. I would rather ask and be sure than guess and mess up later!

Now if I can just learn to type!

[Mariss Freimanis]

pminmo,

I'm just guessing but there may be room for improvement.:-) I notice you are a behavioral coding kind of guy. I'm a total resources used control freak so I'm a structural coding type.

That means I work out a logic schematic first, then massage it to reduce gate and register count to the minimum. Logic diagrams go a long way in giving clues where reduction is possible. Only when everything looks pretty do I start translating the schematic into code.

The drive design of the tutorial will have four sections:

1) Phase generator. This generates the counters and logic needed for one full electrical cycle of microstep counting.

2) T-base. This is the timebase generator. It sets the switching frequency of the drive, synchronizes the switching frequency phase to the step pulse rate and generates a ramp waveform needed for feed-forward compensation.

3) Sincos. This takes the output of the counters in (1) and the time base in (2) to generate a sine-cosine waveform data and output it as sine and cosine current references.

4) Phase Drivers. These are the motor current switching regulator logic that use signals from external comparators and from the T-base (2) and Phase generator (1).

Mariss

[tony ennis]

Mariss, here's yer d-flop

module DF (input C, D, output Q);
reg X = 0;
always @(posedge C)
X <= D;
assign Q = X;
endmodule

Could you do the assignment of Q as part of the always:

always @(posedge C)
assign Q = D

?

[pminmo]

Really looking forward to the rest of the tutorial!!!!!!!!!!!!!!!!!!!!

[amplexus]

I dont understand where these numbers come from

The results are very close to ideal. The vector sum is 1 +/-0.01% and the resulting angles are:

08.98 degrees instead of 09 degrees
27.01 degrees instead of 27 degrees
45.00 degrees instead of 45 degrees
62.99 degrees instead of 63 degrees

I can add vectors at least graphically but am unclear what vectors you are adding. I realize it is just confirming your design matches the real world but I need to understand how you came up with the double check.

Your homemade dac is indeed a clasic, and Your implementation provides some insights as to how you think about design. some clever stuff and much more subtle than my brute force approach.

The reciruculate mode is a nice addition. One less puzzle to work out but not to worry you have still left me with plenty more.

I cant wait for chapter 3 an beyond

Amplexus Ender

[Mariss Freimanis]

Here's Chapter 2. It's a rough draft, just like chapter 1.

Mariss

[pminmo]

Here's Chapter 2. It's a rough draft, just like chapter 1.

Mariss

Rough, no way, tons of great information!!! I'm really excited about this, something I haven't felt for a while...

[Mariss Freimanis]

5/32, 15/32, 23/32, 29/32 and 32/32 are the closest approximations for sine of 9, 27, 45, 63 and 81 degrees if the numerator must be an integer and the denominator must 2^5.

Lets take 15/32 and 29/32; an approximation for sine and cosine of 27 degrees.
15/32 = 0.46875 and 29/32 = 0.90625
Vector length = SQRT(0.46875^2 + 0.90625^2) = 1.0203
arcsin (0.46875 / 1.0203) = 27.35 degrees instead of 27 degrees

08.88 degrees instead of 09 degrees, vector sum is 1.01 instead of 1.
27.35 degrees instead of 27 degrees, vector sum is 1.02 instead of 1.
45 degrees uses 23/32 for sine and cosine, vector sum is 1.02 instead of 1.
62.65 degrees instead of 63 degrees, vector sum is 1.02 instead of 1.
81.12 degrees instead of 81 degrees, vector sum is 1.01 instead of 1.

I did the above with a calculator. In the pdf I used ACAD (draw a vertical line 15/32" long, draw a horizontal line 29/32" long from the base of the vertical line, draw the hypotenuse, have ACAD measure the angle.) My problem was I had limited the ACAD precision to 3 decimal places. This gave overly rosy results and I will revise the pdf.:-)

Even so, the worst electrical degree error is 0.35 degrees. This is equivalent to 0.007 degrees mechanical on a perfect step motor. A very good real-life motor is accurate to +/-3&#37; of a full step or about +/-0.05 degrees mechanical. The drive accuracy is over an order of magnitude better.

While starting this reply early this afternoon, I had a brain flatulence. It occurred to me that we can offer the upcoming G250X/G251X and G201X drives with any microstep resolution from 1 to 16. Just for fun I wrote-up Verilog code for a 16 microstep G250 and tested it. It ran pretty as could be and it took only half an hour from idea to running drive. So what I will do for fun tomorrow is write code for every resolution between 1 "microstep" (a full-step drive) and 16 microsteps.

If for instance a 13-microstep drive rocks your boat, we will have code for it.

Mariss

P.S. I haven't posted the SINCOS and DAC section yet. Where did I slip saying how it works?

[amplexus]

The sine cos question came from chapter 2 mostly, I have read pretty much all of your posts both here and on yahoo and have been thinking about various ways to impliment your ideas without copying them directly. Curiously I spent part of the evening generating sine values from 5 to 10 microsteps. I use the graphical approach for vector addition, but if there are accuracy problems I may need to take a different approach. All this stuff may force me to finally learn to use mathematica. Would the 6 microstep be multiplied by 2^6, 7 microstep by 2^7 etc?
As to the diy dac a number of people have published it with some variation including Bob Pease and I think Don Landcaster or Forrest Mims.
Amplexus Ender

[Jay C]

It occurred to me that we can offer the upcoming G250X/G251X and G201X drives with any microstep resolution from 1 to 16. Just for fun I wrote-up Verilog code for a 16 microstep G250 and tested it.

Mariss, I did some analysis (while I wait from my kit) on the 5 microstep sine cosine angles as I want to see if starting at 9 degrees was optimal or if it was an arbitrary point halfway from the electrical step angle of 18. Turns out is it optimal. Thus my question to you is did you do a similar analysis or is there something more simple I'm not seeing? As a check I plan to analyze the other microsteps. I have done 6-usteps and I'd like to know what angle you would start with for that version?

Jay

[JaC]

My first post - and I can't think of a better time to say I'd really like to thank Mariss for making this tutorial. This tutorial was the magic ingredient that pushed me to finally make a stepper drive and learn more about them.

It's been a few years since I did any design with CPLDs so this was also a great way to reaquaint myself - using Verilog instead of VHDL as I used to. It was fun and interesting enough that I don't even remember learning

***** Thanks Mariss! *****


I can second that it does work, although I am having a few problems that someone here may be able to help out with. I am new to the stepper motor drive design and am lacking experience. I am quite sure the problems are my lack of understanding the fine tuning aspects or else my board, not the tutorial.

As I was trying to discover the source of some of my problems, I noticed something to add to Phil's corrections - when you alter the STBY line, you should also alter your DUMP line, otherwise it ramps only when in standby mode. I believe the Time Base section should now read:

DFLOP F12 (.C(CLK), .D(G24), .R(0), .CE(1), .S(STBY), .Q(Q12));


If anyone could offer some help or suggestions, or even just provide a basic 'test gear' list (I see Mariss uses at least 1 motor with the rotor glued to the stator) I would really appreciate it. I don't have a current probe - any suggestions? I may be willing to buy a current probe if someone can recommend one that is not overly expensive if that is a 'must have' tool for this type of work. Mariss has some very nice scope pics of waveforms with current on one axis - mine using voltage probes look like noise...


Quick background:

A few days ago I threw together a board to plug into one of the headers of an XC2-XL kit I ordered for this project. I use the onboard XC2C256 chip since it is already there, is big, and I plan on continuing to modify the drive as I try new things out and learn. A side benefit is that I can map internal signals I want to have a look at through a different header to put a scope probe on. I do have a digital oscilloscope for troubleshooting (TPS2024). If one of you gurus thinks I should be looking at a particular area(s) in one of my dusty textbooks, please point and I will happily dig them out.

ok, so that's my setup - here's my questions if someone can shed some light:

1) The motor sounds and runs horribly at low rpm - in fact stalls and jitters at some frequencies. It smooths out at higher rpm (about 60 rpm) and then runs ok through what I'm guessing is its midband resonance with some noticeable sounds emitted, then excellent after that. Does this mean my sine/cosine waveforms are not very good? Any ideas where to start?


2) The curent set value - I am using a sense resistor of 0.05 ohms, so at 1A there should be 50mV across it. I have been adjusting the current set value to 50mV as well, since this is what is being compared in the LM393 ( A tad higher actually as I see I will lose approximately 1/10th of my set value through the divider at the input). Is this correct? The noise I am reading on the signals while the drive is running practically buries that. Is this normal? Could be my board layout, although the power sections have plenty of trace width and a pair of 680uF caps. I also beefed up the traces with wires as part of my troubleshooting - no effect. I've replaced the .05 ohm with a 0.2 ohm so that I can reference a 200mV signal at 1A - a bit better but not great.

3) The dc bias being added to the pwm sine/cosine reference - I've just been trimming this by sound of the motor .. can someone with experience let me know what I am looking for? Should I expect to see a decent waveform after the filters (ie on the inputs to the comparator) and adjust the peak of the waveform to 50mV?



Half of my issues are likely because I can't get much in terms of useful readings (that I know of) so I can't troubleshoot what may be a problem - the other half being I'm not too sure what I'm looking for


Thanks for any help!

[pminmo]

As I was trying to discover the source of some of my problems, I noticed something to add to Phil's corrections - when you alter the STBY line, you should also alter your DUMP line, otherwise it ramps only when in standby mode. I believe the Time Base section should now read:

DFLOP F12 (.C(CLK), .D(G24), .R(0), .CE(1), .S(STBY), .Q(Q12));

Thanks for any help!

See post 173. It does go into generating ramps when STBY charges high. I think I keep getting confused as the verilog and the schematic differ. The schematic shows STBY connected to RESET, the verilog connects it to SET inverted. The DFF RESETS and SETS on HI. Thus when STBY is LO, the verilog sets Q HI and drives DUMP to a hard LO. When STBY goes HI, F12 starts acting on the clk and G24 toggling between a hard LO and tristate for the DUMP ramp.