[Mariss Freimanis]

Mariss why did you go with Verilog over VHDL?

pminmo,

Let me add to what Marcus wrote. The attached thumbnail shows a simple but practical quadrature decoder. I'm using it to illustrate how a 4000-series CMOS logic circuit migrates to a CPLD implementation.

It's of paramount importance to minimize gate package count when using discrete logic. 4000-series CMOS logic lends itself well to analog RC timing elements and I believe the 3 XNOR gate circuit is as simple of a quadrature decoder as is possible. It is used in the G320 servodrive.

Going to a CPLD implementation requires a change in thinking when designing a circuit. Far more gates are available but good practice requires a fully synchronous design. This requirement adds to the complexity of the circuit when compared to an asynchronous design (the CD4077 version). Additional complexity results from not having RC generated time delays available.

The CPLD implementation is an equivalent of the 4000-series circuit. You should be able to see it in the red, blue and green highlighted areas. 3 XOR gates are still needed but it 'grows' by 5 D-flops which generate the time delays and insure synchronous operation.

The Verilog code shows how simple it is to convert the CPLD tailored logic schematic into very brief code. The top module 'QUAD_DECODER' declares all external inputs and outputs, The D-flop connections described next, boolean operators ('^' is the 'XOR' operator) complete the connection description and the STEP and DIR outputs are assigned. The module 'F_D' is a behavioral description of a D-flop. It functions similarly to a subroutine; defined only once, it is 'called' in F1, F2, F3, F4 and F5.

Mariss

[pminmo]

I'm more familiar with VHDL. VHDL trips me up frequently as my brain is more locked on top down software programming, so I sometimes forget that it's a behavioral model not program flow. For example "if then else" is both C and VHDL so the old brain cells are more in gear with software programming. I have an old friend that does instrumentation for a physics department at a local university. It involves a lot of high speed parallel acquisition. He's still doing schematics, but the professors are pressuring him to do VHDL since that's what the EE students are being taught. I wonder if Verilog is as easy get the same software logic confusion I fight.

[CoAMarcus]

Well, there are bits of Verilog that are still a mystery. For instance, I do not completely understand what exactly a macrocell is composed of or how to minimize them in the code, but we are getting there. I know some C, and am just not a fan of it. I much prefer Verilog, and I think Verilog is geared more towards those who are not programmers, and VHDL is geared toward those that already know some other language.

-Marcus Freimanis

[davo727]

Hi, How is the G380 project coming along? Mulling buying 320s or waiting. Thanks, Dave

[kreutz]

Well, there are bits of Verilog that are still a mystery. For instance, I do not completely understand what exactly a macrocell is composed of or how to minimize them in the code, but we are getting there. I know some C, and am just not a fan of it. I much prefer Verilog, and I think Verilog is geared more towards those who are not programmers, and VHDL is geared toward those that already know some other language.

-Marcus Freimanis

CPLD architecture is based on logic blocks, each logic block contains a PLA array that generates control terms, and macro-cells for use as resets, presets, output enables, asynchronous clocks. Other product terms are used as individual inputs for each macro-cell.

Macro-cell architecture is vendor and family dependent. Each macro-cell supports combinational, or registered inputs, Flip-flops D, T, or latch, preset, reset, etc. If a macro-cell needs more product terms it can get them from the PLA array.

As a designer, you could make better use of the internal CPLD architecture by knowing its resources and optimizing code in order to make better use of those resources. When you simply write a program without knowing the CPLD internals, you let the automated design flow to make the key decisions for you. It works OK if your constrains are met and there is enough space for implementing your code. Going the easy way could require upgrading to the next higher gate count device when proper design would allow you to keep your current CPLD just by going the extra mile.

Another detail, Verilog is known for producing results that simulate OK but are non-synthetizable, that is why I use VHDL. In general, Verilog is easier to use if you keep that detail in mind.


Regards,

Kreutz.

[kreutz]

..... I have an old friend that does instrumentation for a physics department at a local university. It involves a lot of high speed parallel acquisition. He's still doing schematics, but the professors are pressuring him to do VHDL since that's what the EE students are being taught. .....

I still do the same, generally my top document on the project is an schematic. Most of the time I mix schematics and VHDL....

Kreutz.

[Burn]

Just finished buying 3 G320's. Any progress on these?

Question for you Mariss (Or Marcus): Would upgrading from a G320 be worth it once these are released in your opinion?

[jeep534]

Mariss,
I have been following your product for some time (Since early 2004) I have 2 large servo machines 14 amps nominal and 50 peak.. 160 volts max... I understand your market nitch. would it be that difficult With the new architecture to drive a HIGH Current output stage to take advantage of all those boss style servo machines hitting the boneyard....

and as always you have a tremendous product and service


Thanks
archie =) =) =)

[CoAMarcus]

Just finished buying 3 G320's. Any progress on these?

Question for you Mariss (Or Marcus): Would upgrading from a G320 be worth it once these are released in your opinion?

Burn,


The G380 will do the job just as well as the G320. The difference is going to be in the protection it offers. So the short answer is no, you would not have to upgrade. However, if you needed/wanted some of the new features, then it would certainly not hurt. We try to keep all of our products backwards compatible, so there will be limited wiring changes that would have to be done.

jeep,

The drives we manufacture will continue to have the same specs for maximum voltage. We try to keep our own niche in the motor control market, and anything above 80V/20A requires several things: New design, higher tolerance components, and liability insurance. If we make a 100A drive and some guy sticks a fork in it and fries himself, we would run the risk of a liability lawsuit because we didn't explicitly say to not stick a fork in it.

Our drives right now provide a nasty bite if messed with, but not enough to do serious damage most of the time. The chances go up significantly if we were to increase our power ratings.

-Marcus Freimanis

[jeep534]

Marcus,
Fair enough....... point well taken..... It never occurred to me that liability issues would be involved.... I will try not to stick a fork in any of my machines =-)

[davo727]

Hello, Wondered what the status was on the G380 deal? Thanks, Dave

[asuratman]

Marcus,
Do you plan to make 4 axis servo drive like g540. Thanks. Aristo.

[punisher454]

I am also curious about the G380 drivers. I'm currently in the market for 3-6 drivers and I'll be a bit bummed if I buy 6 320's next week and the 380 comes out a few days later.

[CoAMarcus]

The G380 will be undergoing testing for the next several weeks and we will announce the release. It will not be released next week so don't worry about buying the G320s. It will be several months before it is released as we have to wait for PCBs once testing is finished.

Marcus Freimanis

[punisher454]

okay, so if the 380's are at least a few months away I'll probably get some 320's in a week or two.
Thanks for the update on the ETA for the 380's.

[davo727]

Hi, Wondered how these are going? Thanks, Dave

[rokag3]

hello mariss
for the future servo cont "3800"
At least i find out what will should be servo driver of the future.
this was asked by keutz for uhu month ago:

A:the power stage must be modular so you choose the most efficient for your servo

B:for big servo the use of igbt should be systematic I am surprise to see in threading mill they use igbt result no transfo. for us one transfo 2Kw 54V + cap =200 euros

C:full double closed loop the fact that many new rotary encoder using fast electronc can be programmed (CUI) and are low cost and the fact that linear scale see their price going done (dro 1micron glass about 200 $ glass)
The cost of metal + the cost of high precision metal device will push to new machines less rigids and precise the electronic will be in charge to compensate.

D:use of optic fiber (toslink cheaper than shielded cables)for the encoder and all signals this will prevent most of the problems of electro magnetic interferences

E:Must send in real time to the pc flags about how the work is done to have a high level sync
F:index , limits up and down must be used

G: slot for non volatile memory card
to keep data bank for statistic
example :how many Amp used to travel on X with no load 1 month ago
The economy realised on the power supply and the high prec. device will largely pay the added costs

Lucien

[davo727]

Hello, Has the G380 project been round filed?

[mikrokontrola]

Hello Mariss,
I have a question regarding your quadrature decoder (message #21), especially CMOS version used in G320, which I use for retrofitting.
What happens if the encoder changes direction just after edge on A channel. Lets say 0.5us after. It seems that the counter will change their content by 1, but should count 2 pulses, one up next down, or opposite.
I hope I'm wrong
Gregory

[Mariss Freimanis]

Theoretically it can change 1nS afterward but it won't matter; the CH_A and CH_B signals pass through a RC low-pass filter (5uS) which prevents this from causing a problem. The decoder must have at least 2uS between state changes to work reliably. Per your scenario, the input goes high, then low again 0.5uS later. That isn't 'seen' by the decoder because the duration was less than 5uS.

In the CPLD version everything can be ratcheted by nearly an order of magnitude. However it wouldn't be wise to increase the input filter low-pass freq too much. It should remain only slightly in excess of the max step pulse frequency. Otherwise it needlessly opens the system to noise.

Mariss