[pminmo]

Phil,
Your bug crushing skills are indeed impressive. Any chance you would write a simulation and general troubleshooting tutorial for verilog.
thanks for your fixes your contribution is greatly appreciated
Amplexus (Ender)

It was pretty dumb on my part, I knew better but just didn't think to look at the pin setup. Some modes such as weak keepers just don't register. To many years of SSI, MSI logic circuitry.

Right now my time is kind of full. Troubleshooting is more logical thought process than anything. A process of narrowing possibilities to sharpen the focus. For example the issue for me was a current path regarding the STNBY signal as the capacitor rise wouldn't go to the 3.3V rail. So you think through the possibilities, leaky capacitor, bad resistor, bad net, bad gnd, bad 3.3V, etc. You eliminate the the easy, measure 3.3V, ring gnd, measure paths with power off...all were good. Eventually it came to the point of seperating the cpld from the rest of the circuit which made it definitive as a cpld issue. So the possibilites with the cpld, bad verilog, bad IC, bad setup. Modified the verilog and still had the issue, so bad cpld or bad setup. You don't want to pull a vqfp44 without being pretty sure the part is bad. In looking over the compilier results...pin list, equations, etc something triggered my brain to question the tristate as I knew it wasn't truely floating then I happened across I had forgot to define the pin as float.

What is a little irritating is the fact there wasn't a warning from the compilier on the tristate verilog vs. the pin definition. Of course for free (Web ISE) I shouldn't complain.

[Xerxes]

1) You don't need a port on the drive that connects to the PC for setting the PID coefficients. Connectors, cables and interface ICs cost $$$ yet get used only once in many cases.

2) You don't need a program to download what's needed in (1).

3) You can't lose or misplace (2) or the cable in (1) if trimpots are used.

4) Trimpot settings are intuitive. Numerical PID coefficient setting is not.

5) Often it is very inconvenient to bring the drive to the PC or visa versa just to adjust a PID coefficient.

Not forgetting the flip side of things:

6) Proper analog tuning usually requires oscilloscope and signal generator, which are a big investment compared to (1). Those are less common compared to laptops (5) and are less convenient to carry around.

7) Trimpots must have quite narrow setting range to keep them usable. You get much greater adjustment range with digital parameter. Try rotating a trimpot by 0.004 degrees which would equal changing a 16 bit value by one.

8) In many cases also jumpers/DIP switches are needed. They are non-intuitive and error prone compared to software controls.

9) (3) but you may slip screwdriver to powered electronics and have a dead device (or a dead user in the worst case).

Just my 0.02 bits :-)

Tero

[pminmo]

Just thought I'd let the group know, I succesfully controlled a motor this morning with essentially the tutorial verilog with the two noted corrections. :banana: The circuit I had been working on was close enough that with some patch wires and a few (my circuit peculiar) verilog changes I could verify the tutorial verilog code.

I'd personally like to thank Mariss for sharing his knowledge. There were some things in the tutorial that gave me a fresh thought process both about Verilog and motors. :cheers:

Corrections from the tutorial code:

assign STBY = G17 ? 1'bz : 1'b0;

assign G22 = Q11 ^ QC[1];

//////////////////////////////////////////////missing CB3BRE///////////////////////////////////-
module CB3BRE (input UD, R, CE, C, output [2:0] Q);
reg [2:0] u_d = 0;
always @(posedge C)
if (R)
u_d <= 0;
else if (CE)
if (UD) begin
u_d <= u_d + 1;
end
else begin
u_d <= u_d - 1;
end
assign Q = u_d;
endmodule

[Bubba]

Phil
Congratulations :cheers::cheers::cheers::cheers::cheers::cheers:
Have a few on me.


Maybe I can do something soon also!

[amplexus]

Congradulations Phil,
Always nice to see things run. And you are right a huge thanks goes tpo Mariss for sharing this (and also to you for helping fix the code). without you two I would still think steppers were simple devices that moved a step each time you pulsed them. And on the other hand I wouldn't be addicted to trying to learn their nuances. It's an uphill climb to catch up to the old timers but I am gaining..
Amplexus (Ender)

[Jay C]

Better late than never, my kit is enroute from Digikey. I miss digital design (though maybe not 5x5 K-maps). I appreciate the excuse to learn something new.

Jay

[Jay C]

It occurred to me that we can offer the upcoming G250X/G251X and G201X drives with any microstep resolution from 1 to 16. Just for fun I wrote-up Verilog code for a 16 microstep G250 and tested it.

Mariss, I did some analysis (while I wait from my kit) on the 5 microstep sine cosine angles as I want to see if starting at 9 degrees was optimal or if it was an arbitrary point halfway from the electrical step angle of 18. Turns out is it optimal. Thus my question to you is did you do a similar analysis or is there something more simple I'm not seeing? As a check I plan to analyze the other microsteps. I have done 6-usteps and I'd like to know what angle you would start with for that version?

Jay

[JaC]

My first post - and I can't think of a better time to say I'd really like to thank Mariss for making this tutorial. This tutorial was the magic ingredient that pushed me to finally make a stepper drive and learn more about them.

It's been a few years since I did any design with CPLDs so this was also a great way to reaquaint myself - using Verilog instead of VHDL as I used to. It was fun and interesting enough that I don't even remember learning

***** Thanks Mariss! *****


I can second that it does work, although I am having a few problems that someone here may be able to help out with. I am new to the stepper motor drive design and am lacking experience. I am quite sure the problems are my lack of understanding the fine tuning aspects or else my board, not the tutorial.

As I was trying to discover the source of some of my problems, I noticed something to add to Phil's corrections - when you alter the STBY line, you should also alter your DUMP line, otherwise it ramps only when in standby mode. I believe the Time Base section should now read:

DFLOP F12 (.C(CLK), .D(G24), .R(0), .CE(1), .S(STBY), .Q(Q12));


If anyone could offer some help or suggestions, or even just provide a basic 'test gear' list (I see Mariss uses at least 1 motor with the rotor glued to the stator) I would really appreciate it. I don't have a current probe - any suggestions? I may be willing to buy a current probe if someone can recommend one that is not overly expensive if that is a 'must have' tool for this type of work. Mariss has some very nice scope pics of waveforms with current on one axis - mine using voltage probes look like noise...


Quick background:

A few days ago I threw together a board to plug into one of the headers of an XC2-XL kit I ordered for this project. I use the onboard XC2C256 chip since it is already there, is big, and I plan on continuing to modify the drive as I try new things out and learn. A side benefit is that I can map internal signals I want to have a look at through a different header to put a scope probe on. I do have a digital oscilloscope for troubleshooting (TPS2024). If one of you gurus thinks I should be looking at a particular area(s) in one of my dusty textbooks, please point and I will happily dig them out.

ok, so that's my setup - here's my questions if someone can shed some light:

1) The motor sounds and runs horribly at low rpm - in fact stalls and jitters at some frequencies. It smooths out at higher rpm (about 60 rpm) and then runs ok through what I'm guessing is its midband resonance with some noticeable sounds emitted, then excellent after that. Does this mean my sine/cosine waveforms are not very good? Any ideas where to start?


2) The curent set value - I am using a sense resistor of 0.05 ohms, so at 1A there should be 50mV across it. I have been adjusting the current set value to 50mV as well, since this is what is being compared in the LM393 ( A tad higher actually as I see I will lose approximately 1/10th of my set value through the divider at the input). Is this correct? The noise I am reading on the signals while the drive is running practically buries that. Is this normal? Could be my board layout, although the power sections have plenty of trace width and a pair of 680uF caps. I also beefed up the traces with wires as part of my troubleshooting - no effect. I've replaced the .05 ohm with a 0.2 ohm so that I can reference a 200mV signal at 1A - a bit better but not great.

3) The dc bias being added to the pwm sine/cosine reference - I've just been trimming this by sound of the motor .. can someone with experience let me know what I am looking for? Should I expect to see a decent waveform after the filters (ie on the inputs to the comparator) and adjust the peak of the waveform to 50mV?



Half of my issues are likely because I can't get much in terms of useful readings (that I know of) so I can't troubleshoot what may be a problem - the other half being I'm not too sure what I'm looking for


Thanks for any help!

[pminmo]

As I was trying to discover the source of some of my problems, I noticed something to add to Phil's corrections - when you alter the STBY line, you should also alter your DUMP line, otherwise it ramps only when in standby mode. I believe the Time Base section should now read:

DFLOP F12 (.C(CLK), .D(G24), .R(0), .CE(1), .S(STBY), .Q(Q12));

Thanks for any help!

See post 173. It does go into generating ramps when STBY charges high. I think I keep getting confused as the verilog and the schematic differ. The schematic shows STBY connected to RESET, the verilog connects it to SET inverted. The DFF RESETS and SETS on HI. Thus when STBY is LO, the verilog sets Q HI and drives DUMP to a hard LO. When STBY goes HI, F12 starts acting on the clk and G24 toggling between a hard LO and tristate for the DUMP ramp.

[JaC]

See post 173. It does go into generating ramps when STBY charges high. I think I keep getting confused as the verilog and the schematic differ. The schematic shows STBY connected to RESET, the verilog connects it to SET inverted. The DFF RESETS and SETS on HI. Thus when STBY is LO, the verilog sets Q HI and drives DUMP to a hard LO. When STBY goes HI, F12 starts acting on the clk and G24 toggling between a hard LO and tristate for the DUMP ramp.

ok - this is part of my being new to this - I thought when out of standby, we wanted ramps (ie when stepping), not the other way around. I guess I don't understand what the ramps are really there for. I'll look into it more.

Thanks!

[Mariss Freimanis]

Ja C,

Thank you for the nice comments. About the sine-cosine thing; I'm not sure if I understand your question. The sine and cosine DAC outputs use a two-way symmetry to economize on resources. Sine and cosine from 0 to 90 degrees is mirrored at the 90 degree axis to generate these functions from 90 degrees to 180 degrees. Being mirror images, the initial offset is 1/2 of the electrical angle, 9 degrees as you pointed out.

The sequence then becomes sincos of 9 deg, 27 deg, 45 deg, 63 deg and 81 degrees. Unfolded at 90 degrees, magnitude continues on as 99 deg, 117 deg, 135 deg, 153 deg and 171 degrees. The second fold of symmetry is the sign and the 2-bit counter instructs the bridge on the direction of current flow (sign). Sine 180 degrees to 360 degrees is a repetition except the sign is reversed.

The general solution for an "n" microstep drive is calculate sine-cosine of (90 degrees (i + 0.5) / n) where i is an integer between 0 and n-1. I cannot think of another trig sequence that mirrors at 90 degrees (first fold) and 180 degrees (second fold) except this one.

A further "simplification" would have been to solve sine and cosine only over a 0 to 45 degree span, then swap sine with cosine from 45 degrees to 90 degrees. Elegant though it is, the "swap" logic is takes more CPLD resources than the brute-force method of solving sincos over the 0 to 90 degree span. The idea is to find the resource minima point for the entire design.

About VHDL versus Verilog: My understanding is a "real" programmer would never use Verilog and I know a few as friends. Verilog is intended for low to medium complexity projects while VHDL is suited for medium to very complex projects. Anything that fits inside a 32-macrocell CPLD is definitely low complexity.:-) The entrance fee you pay for Verilog is much lower than for for VHDL. I'm a lazy person (put out only enough effort sufficient for what needs to be done) so I chose to learn Verilog over VHDL. Lazy, but it works given what has to be done.

About your board problems: The mission of the Verilog Tutorial was how to use Verilog to design a working microstep drive, not "How to Design PCB Motor Drive Layouts that Really Work".:-) Board layouts need as much skill and care as designing a circuit or writing the code for a CPLD. Many people neglect it to their sorrow.

The most elementary mistakes are skinny traces, 2-layer boards, haphazard daisy-chained grounding and supply distribution, a wanton disregard to supply bypass capacitors and no concept of Kelvin connections to the really important stuff. That gets most of it.

Most people think of board connections as if they were superconductors. They aren't. Think of board traces as if they are a sheet resistance (kind of like carbon paper). They have real resistance and inductance. It's tough to accurately extract a 50mV signal (1A through 0.05 Ohms) from a power MOSFET circuit that has 30A shoot-through currents (diode reverse recovery) that can easily generate 2 to 5V noise. Bad signal to noise ratio unless you know what you are doing.

Signs you are not doing things right: If your board shows FR4 (fiberglass epoxy) green, you aren't doing things right. Bare fiberglass is just that; bare where it could have been covered with current carrying, low resistance copper foil. Learn to hate the color green. Green is inefficiency, green is not non-conductive, green is an area that could have been electricity conducting copper. Why etch all that good copper away?:-)

If you use Spice to simulate circuits, replace every conductor with a 0.01 Ohm resistor. See how your circuit simulates then. Be prepared for a major shock.

I did a few posts on correct board layout in the power section of a drive. It dealt with Kelvin connections in the vital parts of the circuit layout. I don't remember the thread or the time because it was a quickie toss-away. Maybe someone here can recall when and where. It was useful and instructional.

Sorry for the rambling post.

Mariss

[Jay C]

I appreciate you answering my questions about the sine cosine table ... but just so you know JaC is not Jay C Tho I certainly appreciate your taking the time to write up and share as well

Jay

[Mariss Freimanis]

OK. I should learn how to read.:-) I'll try it sometime.

Mariss

[JaC]

Thanks again Mariss,

I had to mechanically etch my board on two layers - not the best for sure. It's standard FR4, 1oz copper. I have attached a pic with the top and bottom view for anyone to criticize who cares to The whole bottom is ground plane except where there are traces of course. The top shows some jumper wires to decrease the resistance (black wires). The others are me just trying stuff out. When prototyping, I like to keep all components on one side and spaced out if possible for easy debugging - no flipping the board back and forth to get at signals. I tried to isolate the power section as best I could from the low-level signals. I have lots of SMT parts on hand which is why I went that route.

Perhaps I'll lay out a proper 4 layer board and have it made if it looks like that could be the problem here. I'll wait a couple more days to see if there are any more suggestions for me to try out, then I'll go ahead.


James

[pminmo]

Here is mine. I too wanted to spread it out, except each H-bridge is tightened up as much as I felt I could and still solder without a solder mask. Mosfets mounted on bottom. Power gnd plane on top, heavy current traces and power plane on bottom.

[amplexus]

I hunted a bit for the power layout posts but cnc zone has a rather crippled search, any idea where they might be posted? I would love to read what you had to say about kelvin connections and shoot through current problems.
Amplexus (Ender)

[amplexus]

Phil,
Nice looking board. Is this a working 2 sided board? Did you etch or mill it yourself? The board looks to be Phenolic, or is it really fiberglass?. Is this a toaster oven reflow or did you hand solder it? Would you consider posting the trace layouts? I am working on a 4 layer in Eagle but if it can be done with a 2 layer in house that would be better still.
Amplexus (Ender)

[JaC]

Yes, nice work Phil.

Last night I added one more jumper after reading Mariss' response, thinking about layout issues. I jumped from the ground side of the current sense resistors to the power ground terminal, and things cleaned up enormously. I am using 1A 5V steppers, and I underestimated the return path traces when using only 2 layers, but I believe it can work with 2 layers for this size of motor. Phil didn't make that mistake on his layout.

[pminmo]

It's a double sided pcb. No I didn't mill it, I could have but when you get this complex, without through hole plating, it's just too much fab bother. Fabrication is Advanced Circuits bare bones pcb's.

[lucas]

I did a few posts on correct board layout in the power section of a drive. It dealt with Kelvin connections in the vital parts of the circuit layout. I don't remember the thread or the time because it was a quickie toss-away. Maybe someone here can recall when and where. It was useful and instructional.

Mariss

Is this the one you are looking for?

http://www.cnczone.com/forums/showpo...8&postcount=89

I tend to keep a link to "useful and instructional" posts.

Regards,
Luc.