Hi Max,
I have a couple of questions about the code in YAPSC_MERGED. They are probably pretty dumb but I like to understand how things work!
In timer1.c line 89 cmd_posn is set to POSCNT+1. Why +1?
Step and direction inputs use input capture ISRs (IC1 and IC2). I am thinking of using CN0 (pin 12) for direction change and T2CK (pin 11) to count on every edge for step input (need to change UART to pins 17 and 18). This would eliminate ISR overhead on step pulse. Counter would be used to update cmd_posn and be cleared on direction change and in servo loop interrupt.
What do you think of this? I do not have a lot of experience coding dsPIC!
What are the differences between DEMOBOARD and YAPSC V1
It seems that pwm.c is set up for all n channel mosfet h-bridge and for high-side p channel mosfet I should change high-side output polarity to active low. Is this correct?
Many thanks for your consideration.