[Episs]

Are there anyone who knows something about FPGAs and are building some CNC motion controller + driver (all in one) ??
I am asking becose I am traying to build that kind of system by myself whith Alteras Cyclone II EP2C8F208C7 and curently I am in PCB making stage ( I am making base universal PCB module on which I could add other modules with hardware in future for experiments and code development.
And what do you think about Alteras new Cyclone II dev.kit for 150$ maby I should buy this kit for code debugging and error checking in code, becose FPGA bord which I am making will be 2 layer and I will solder it my self so if code will not work in real life then it would be esear detect erors using cyclones II dev.kit .
Here is my last PCB drawing I made it is not completed yet. There are mising power suply, osc. config. (EPCS4) and JTAG pins not conected!

[xyz100]

Normally FPGAs are debugged with software simulators, not in real hardware.

The flow is:
1. Write the code in VHDL or Verilog;
2. Write testbench in VHDL or Verilog;
3. Simulate/test/debug the code. There are some free simulators (Ikarus for verilog).
4. Synthesize and place and route the code for target FPGA. You would have to pay for these tools (most likely)
5. Load the compiled file in the FPGA's configurator (you need a configurator to load FPGA).

Overall, I think the development will require significant initial investment.

[Episs]

Now I am just serching all information which is availible on the net.
Which IP processor to chose for motion controller there are several options like Alteras Nios II, Latticemicro32(is for free), or one of opencores.org free availible processors for example there was AVR atmega 103 compatible core. Previosly I used ATmega128 and already wrought lot of code in ASM traying to make motion controller on atmega128 but I didn't make becose of low peripheral count so I switched to FPGAs. so I need to chose one processor Core.
I will wright in VHDL.

[pastera]

Where will you put all the memory you will need to hold the G-code?
FPGA's are extremely expensive when compared to a general purpose processor (8051). If a microcontroller can do it, and it can, then it would be cheaper to place the bulk of the processing in the uC and use one or two CPLDs for the high speed logic that the processor can't handle.

Aaron

[Episs]

I will use parallel flash memory 32Mb (16bit) atmel AT49BV322
I think 32Mb would be enough for G-code and procesor code storage.
About processors then they are not so cheep as compared to FPGAs for example Atmega128 is about 16$, we can take more powerfull AT91SAM7xx ARM7 core about 11-12$ and all they have is Flash memory that my FPGA don't have and Fpga costs are: EP2C8F208C7 20.3$ in digikey +configuration Flash (there are lot of options we can use EPCS4 (16$) or some simple MCU like Atmega48 1.5$+SPI cheep Flash 3$=4.5$) so totaly working FPGA in cheapest configuration will cost about 25$ and it is just 2X more than single MCU but in FPGA we can put 3 Mcu cores (like Nios II) + logic so we get higher price/perfomance ratio. Actualy there is one cheep FPGA motion controller it is MesA FPGA anything IO card but I need sutch electronic which I could modify by my needs and with more logic capacity.
And FPGA is more flexible and If wouldn't like Nios II core then I can downlode any other core and reconfigure fpga so I can evaluate diferent free IP-cores and choose the best for my design. This reconfiguration feature is what I need.

[pastera]

Your development costs for an FPGA solution will be much higher if you choose to place the microprocessor in the FPGA. Unless you are planning on building many thousands of unit, you wouldn't recoup the non-recoverables.

If you are doing this as a learning project, you will add a lot to your resume if you even get to 50% completion.

Aaron

[Episs]

It is as Lerning project DIY, where I plan to make some useful electronic which I could use for my CNC needs + experiments.

[xyz100]

FPGAs with built-in cores or IP cores do heve built-in RAM (so called RAM blocks). If I remember correctly they can be pre-loaded with code during configuration. Usually configuration data stored in serial EEPROMs (Electronically Erasable Permanent Read Only Memory). Sometimes Flash is used which might be more sutable for your design. However it will require external loader (small CPLD). The benefit - same Flash can hold both FPGA image and CPU executable.

[daedalus]

hi, i looked into doing something similar a while back. One place i suggest you look is opencores.org, as they have a fair bit of free IP, including soft core processors and networking / io IP available.

If i were you i would get a premade fpga dev kit, and start with that. IIRC the cheapest supplier i could find was a board called Raggedstone, its pci based, and the same company has several models to suit your budget / needs, basic one starts around the $100 mark. There are tutorials available for using the opencores pci IP with this card, but cant remember where i found them.

[xyz100]

hi, i looked into doing something similar a while back. One place i suggest you look is opencores.org, as they have a fair bit of free IP, including soft core processors and networking / io IP available.

IMHO code at www.opencores.org is extremely rought. It will take a lot of effort to make it work. Might as well write your own code.

[daedalus]

xyz100: guess it depends on your time and ability, i was looking at doing a pci based board, and writing a pci master core is way out of my league

[Episs]

This week I made my first VHDL code for Quadrature encoder logic this code detects encoder rising edge and faling edge and sends one clock signal this logic totaly take 21 LE next I will put alteras megafunction up down Counter and timer and logic will be compleated + direction sens logic.
I checked this Onpen core Quadrature decoder and ather free availible decoders and all they do is counting up and down + direction but what i need is a time interval to establish encoder rotational speed so this was a hardest thing to do to make this rising and faling edge detektos like microcontrolles external interupt which detekts rising edge and make interupt signal ass soon as posible (my logic will work mutch faster then simple MCU I testes in waveform simulator 100Mhz clock signal and there was no problem so teoreticaly I could detect some 20-10Mhz encoder signal and mesure signal time.
About PCB then I know that there is one great boord like alteras Cyclone Dev.kit for 150$ but thing was that this bord came out too late when I already bought from digikey my FPGA ep2c8f208. And now i have this chip and there is no way back. maby in later i will buy this alteras bord becose it has Ep2C20 chip with more logic and aditonal features

[Episs]

here are some waveform picture there CLK is 10ns (100Mhz) I tested also CLK=7ns and it worked but below 7ns it start to miss encoder signal and time to capture signal is 2 CLK cycles.


and here is logic RTL picture

[Episs]

I made some improvement to input capture module and now it is faster and use DFF insted of data Latch.
Also add timer and counter and FIFO memory here are waveform picture.

Atrums_IN = timer that counts clock signals and when new event ocures it will save value to FIFO memory and will start to count from zero once again so we get encoder rotation speed.
There is block editor picture were is timer,counter, and fifo block + my Encoder1 block


now I will work on avalon buss interface to add encoder module to Nios II procesor core.

[Mariss Freimanis]

The quadrature decoder seems unnecessarily complex to me. The attached .gif shows what's used in the G-Rex including digital noise filtering on the CH_A and CH_B quadrature inputs.

The encoder counts are summed to a U/D counter which is read-out at a fixed INT rate. A difference is taken from the previous value and this difference is summed to a 32-bit encoder position register.

Mariss

[Episs]

Hm I don't think it is too complex there are just Edge detector + timer + counter (FIFO I will remove) and + later will add direction decoder + Avalon interface to conect decoder to nios II procesor core.

It looks like your logic don't have timer. How are you mesuring encoder speed ??

[Mariss Freimanis]

Normally encoder speed is not something that needs to be measured but you can do if you want. Simply difference the current count from the previous one. If this differencing is done at a constant rate then:

Vel = (Cn - Co) / Ts

Cn is the new count, Co is the old count and Ts is the sampling period.

Mariss

[Episs]

But there is a still a Qyestion how can you know Ts (smpling period) if you don't have timer on your system ???
Previously I tried to make sutch motion controller in Atmega128 microcontroller and found out that all these hardware unimplemented peripheries (encoder decoder) take a lot of software resources (code) and processor time to calculate and of course main processor code gets bigger and more complex. now using FPGA I want to simplefy things implementing as mutch As I can in hardware and leave processor just main controlling functions and calculations.

[Mariss Freimanis]

I'm assuming your FPGA is clocked. That is your timer when divided down.

Mariss

[Episs]

I Think timer is device that counts Clock signals (like a counter but now it counts Clock insted of encoder steps) and when you need elapsed time count you just go and read timer value but If we have diveded Clock than there is no device that counts clock signals it is just low speed clock.