[fahque99]

I was looking on digikey and its $3.82 each CAD. I will have to see how much future charges to ship, thanks.

[boldive]

I will have to see how much future charges to ship, thanks.

$7.50CAD all around Canada. For me, If I will place order before 3:00pm I will get parcel on next day before 3:00pm (FedEx delivery).

Digikey is the most expensive online store in the Internet.

[ekocakaya]

I got the how to make the microstep table thank everybody.

I want to ask , if I want to make 1/256 microstep table ,and want to run the motor with 1500 rpm , what kind of cpu should I select or how much MIPS should be? ADC or DAC resolution ??? for 256 microstep its enough 10 bit

Also How we write look up table in verilog ? can anybody send an example

Happy New Year

Erkan

[boldive]

I want to ask , if I want to make 1/256 microstep table ,and want to run the motor with 1500 rpm

If you want to do this, please read this first.

1/256 microstep is useless. If you want to run motor at 1500rpm 1/256 microstep I would redirect your question to Google: stepper motor control theory.

[ekocakaya]

Thank u for quick reply , I read it yes you are right , 1/256 for 1500 rpm useless. But I only want to learn its technique for cpu and dac selection?

In chinesee step drivers they have 1/256 step dip switches and current switches , how they change the current , I look up inside the driver there is Xilinx CPLD and also some IC like LM339 LM358 IR2104 IRF640 but some of chips labels is erased . They are very smart , What are these chips do you think????

[tecfacet]

Hello All...

On another thread, Mariss has offered to give us gerbers for his cpld development breadboard. I am interested.

Would anyone else like to join me for volume buy of pcb's? Does anyone buy boards often?

Great information here and talented people also.

Thank you Mariss and all the others that contribute.

Roger

[blazevski]

Hallo

I need your help, i like to make my own drives but i can't find any shemas for doing that. The problem is that i am new in this business. I'v got unipolar 4A stepmotors. I'v posted the same question in CNC DRIVES but they redirect me here.

Thanks

[boldive]

Hallo

i can't find any shemas for doing that.

Schematic is in the CPLD Tutorial. Tutorial is in this thread.

[H500]

I would like to thank Mariss for the tutorial. I originally implemented a fixed time off design in VHDL. Unfortunately, I had to take a 1 year hiatus from this hobby. Now I could not find the code and also I realized that my newly acquired knowledge of VHDL has faded due to the lack of use. The tutorial will be extremely helpful. I'll learn Verilog this time.

[Mariss Freimanis]

Happy New Year. Here are the promised breadboard gerber files.

Mariss

[cnckone]

Hello,

First, let me express my warmest thanks for making this tutorial.

For some time now I have been planning a CNC controlled mill project and decided to start with the basics, ie. getting some step motors to run. I had a microcontroller based design already running PWMs but decided to drop that in favor of some mixed signal circuitry. I already had my own logic/analog based design on the paper until I found this thread while doing information search on motor controllers. The given verilog example code saved me few weeks of my time.

I know I could have just bought 3 or 4 drives for the cost of tools and components in small quantities for my drive project but where would the fun be then? For an electronics engineer the answer is obvious. Also, knowing that something can be done makes whatever you are doing half done.

Well, to the point. This design as such is useless except for tutorial use but is rather easy to modify for proper 10 microstep operation. However, I am not after for a drive with limited functionality. To my understanding some nice features to add would be interleaving the PWM cycles, stabilisation circuitry and making microstepping sin/cos references to change in order to make the drive full step at higher velocities.

If anyone is interested in stabilisation circuitry there is a couple of patents that provide plenty of information. These have US numbers 4675590 and 4683409. These two should provide enough info to any dedicated person to realise a stabilised step motor drive - there is no need to follow the patents exactly but use them as pointers to right direction. Actual implementation can be done in several different ways. I think these two are the best examples on resonance compensation I found from a rather comprehensive research on stepper drives.

It is quite clear that for stabilisation a frequency to voltage converter and amplified/filtered feedback from current sensing resistors are needed. The delay element is easy to add into the example drive circuit. Latter of these patents has figure 5 which gives one example of a F2V, there element 21 (20 and 21 can be combined to an integrator) being the voltage output. Actual implementation of this can found in step pulse checker circuit I saw somewhere in this site too.

As for gradually changing the references to full step, I found this to be little more problematic at first. If I were to disclose how that can be done might upset someone so I will leave it for now except for a little teaser: The digital part should be as simple as adding one input to an existing gate in the example circuit .

However, I do have a question regarding those using commercial drives with changing reference waveforms: If I were to drive a motor forward with say 10 million steps and then the same amount backwards (with high enough max velocity, identical or different velocity profiles both ways) will the motor rotor return to exactly the same position it started from? In other words, does the reference alteration induce any positional errors?

Once again, thanks a lot for taking time to make this tutorial.

My "full featured" step motor drive is now bits and bytes in schematic/layout software but I will let you know how it works once I get it done.

[boldive]

Mariss, could you give more details about DUMP output?
G24 goes true for 3.2us every 51.2us. F12 S input goes true when STBY is low, for 400us after each STEP pulse.
As a result, after each STEP pulse DUMP output stays in "0" state for 400us and then starts to switch between Z and 0 for 3.2us every 51.2us


DF F12 (.C(CLK), .D(G24), .R(0), .CE(1), .S(~STBY), .Q(Q12));
assign DUMP = Q12 ? 1'b0 : 1'bz;//1'bz : 1'b0
assign G24 = QB[7] & QB[6] & QB[5] & QB[4];


Is it correct?
Thanks.

[pminmo]

Mariss, could you give more details about DUMP output?
G24 goes true for 3.2us every 51.2us. F12 S input goes true when STBY is low, for 400us after each STEP pulse.
As a result, after each STEP pulse DUMP output stays in "0" state for 400us and then starts to switch between Z and 0 for 3.2us every 51.2us


DF F12 (.C(CLK), .D(G24), .R(0), .CE(1), .S(~STBY), .Q(Q12));
assign DUMP = Q12 ? 1'b0 : 1'bz;//1'bz : 1'b0
assign G24 = QB[7] & QB[6] & QB[5] & QB[4];


Is it correct?
Thanks.

see post 189 about dump, and 183 for code corrections.

[boldive]

Q12 operates the output enable on the output driver going to DUMP. This causes DUMP to go low for 3.2uS and be an open circuit the rest of the time.

Or

DUMP generates slope compensation ramps (0V to 2.5V) to stabilize the motor winding current feedback loops. Output shorts to ground for 3.2uS to dump the accumulated charge on ramp capacitor.

Is there any relation between DUMP and Blanking Time?

So, my question. Is it correct that DUMP goes low for the fist 400us of PWM cycle?

[pminmo]

I've kind of forgotten the details, but Dump doesn't become active till stby goes true.

http://www.cnczone.com/forums/showpo...&postcount=189

As I recall when stby goes true, Dump shorts the cap starting a new slope compenation ramp cycle based on the timing decode of G24.

[boldive]

but Dump doesn't become active till stby goes true.
As I recall when stby goes true, Dump shorts the cap starting a new slope compenation ramp cycle based on the timing decode of G24.

STBY goes true when no STEP Pulses. Motor stops. If it is not true, what is the reason to discharge STBY capacitor for 400us after every STEP pulse?
One dump is for Phase A and B for slope compenation when STBY is High (motor is not running.

It looks like something is missing in tutorial or some steps have mistaken explanations. I understand Mariss. He can't give all details about G203V. And I want to say thank you for the start point which he gave us in tutorial.

[pminmo]

STBY goes true when no STEP Pulses. Motor stops.

That is correct.

One dump is for Phase A and B for slope compenation when STBY is High (motor is not running.

That is correct also, so what is it that your not understanding?

[boldive]

what is it that your not understanding?

Phase A and B have 90° phase offset. It has to be one DUMP output per phase.

Why DUMP goes low for the fist 400us of PWM cycle? What it does?

[pminmo]

Phase A and B have 90° phase offset. It has to be one DUMP output per phase.

Why DUMP goes low for the fist 400us of PWM cycle? What it does?

Mariss hasn't answered this thread for awhile so I'll explain my understanding. (it's been sometime since I really looked at the tutorial and I could be wrong...)

Looking at the schematic Mariss provided in the tutorial, dump will generate a fairly linear ramp that will slightly alter the trip threshold of each phase when the motor is stopped. While true, there is a 90 degree phase offset in motor coil currents, the phase current is refelected in the polarity of the H bridge switch and the percentage of current in each phase as determined by the pwm dac.

Dump comes into play when the motor is stopped to diminish the motor hiss that annoys people because of the spurious frequency component.

I believe if you go back further in the thread, Mariss gave a brief explaination of slope compensation for which dump is used.

[brutto]

hi all,
when the comparator goes "0" (current excess the required level) the output pins does reverse the polarity in the H bridge for the rest of the 20khz pulse, and later return to the polarity required or before to this RES pin reset the output forcing all to low and later start the new cicle?
i dont understand in the tutorial how it works because in some part of the tutorial is said RES pin is connected to capacitor + resistor to do a 1 second delay, same as stand by pin.
And I dont see RES pin in the schematic and in other part RES was said as synchronous signal for all when step pin input is received.

I think if you reverse polarity in a low step near to zero current (the first step) it reverse the polarity too much and don't work fine, for example when lm339 low time is longer than lm339 high time into the same pulse.
51us (20khz) - 3.3us blanking time = 47,7us
if lm339 low time is longer than 23us it will have a problem i think.