[shczm]

Hi all,
I add a JTAG connector and two optocouplers to Mariss's CPLD project.
Could anyone help me check the schematic.
Thanks
John

[boldive]

Check value of R2,R5,R6,R7,C9,C10,R25,R27,R29,R30..... too many mistakes. No connection between R18,R20,R23; R24,R26..... How you gonna get +12VDC?
It is better to use HCPL2531 or HCPL2631 for STEP and DIR. Add 200 Ohm resistor on STP and DIR nets.
Try to use TL783 to get 12V and LP2985 (or similar) for 3.3V and 1.8V.

[shczm]

Thanks Boldive,I will redraw and post it later.

[Helmute2000]

Hi,

could you please give me a hint which eCAD designer do you use here?

Thanks!

[boldive]

could you please give me a hint which eCAD designer do you use here?
Thanks!

To do a PCB design - Altium Designer. To develop CPLD - Xilinx ISE Design Suit.

[sonnenenergie]

Nice post... interesting !

Thank you very much for your efforts!!
Greatly appreciated!!!

[tivoidethuong]

could i replace xa2c32 by xc9536 ?

b.r

[tecfacet]

Hello All,

Would someone consider sharing their pcb layout for the cpld stepper driver?

I want to use parts of it for a highschool electronics class.

Thank you,

Roger

[tivoidethuong]

Hi Mariss Freimanis

i cant find RES conect in your shecmatic

b.r

[H500]

It's an optional reset input. It is internally pulled up. It can be left unconnected or to a switch.

[tivoidethuong]

thanks H500


b.r

[danny71]

Hi Mariss Freimanis

What was the software did you use to create the COMPLETE CPLD CIRCUIT?
I tried ISE Webpack but is very difficult to create this circuit: the symbols are not the same as in your circuit, some symbols are not, it is very hard to create bus circuit, …..

Thanks,

Dan

[H500]

The program was done in Verilog.

[Mariss Freimanis]

Dan,

I don't use schematic entry in ISE or in any other programmable logic device development system. I use AutoCad to draw my logic schematics, analog circuit schematics, timing diagrams, printed circuit board layout, solids modeling and all other tasks related to designing a drive.

For CPLDs use ISE to translate from the logic schematic into Verilog and I use Libero IDE for FPGAs. Translating into Verilog from a circuit diagram is mindless, pleasant and easy work. All the hard work is in designing and proofing out the ACAD drawing logic schematic; I already know the circuit will work before I write single line of Verilog code.

I never use a simulator to test the code; in my experience setting up a proper simulation and then interpreting the results is a big and unnecessary pain in the rear. I debug from the target device that is actually running the code. It's attached to the best simulator in the world; real-life motors and real-life analog circuitry. I find this is most time-economical because almost all bugs at that point are syntax or mechanical coding errors (like something going to G37 when I meant G38).

Some things that ease the process is breaking-up the design into seperate Verilog modules along natural function-bock delineations. Each function-block module can be independently tested on the target device (physical motor drive) and pounded into shape until it behaves properly. That way, you know the individual modules work when it comes time to integrate them all together in the main (top) Verilog module. Otherwise you'd go insane tracking a code bug down.

Hope that helps. I'm a little rocky after work; I'm having a glass of fine vintage Cabernet Sauvignon to wind down from a day spent interfacing a PIC24 to an Actel 60K gate FPGA and trying to make them play nice together. Yes, it's the G215 drive and today was like corralling a herd of feral cats.

Mariss

[Mariss Freimanis]

Viola94,

Is there an echo in here? :-)

Mariss

[keebler303]

Viola is a post copying bot with a couple pictures thrown in for spam. Check dear Viola's other posts if you are in doubt.

Matt

[yngndrw]

I know it was quite a while ago that PCB design was brought up, but why are the inner layers better to use for the power distribution in a 4-layer design ?

I thought the inner layers were thinner and would dissipate less heat due to not being exposed ?

[H500]

The planes need to be as continuous as possible. You need to solder components, so that rules out the top layer. You could put one of the planes on the bottom, but if there are any mistakes on your board, it will be hard to make mods. It would also be hard to probe the signals.

The planes are intended for signal integrity and shielding rather for heat dissipation.

[danny71]

Mariss,

Thank you very much for information.
I read this post and your tutorial "5-MICROSTEP CPLD DRIVE" and I have tried to understand your logic in creating CPLD circuit. It's the first time when I have contact with such circuits CPLD. After I understand the circuit, I will try to modify this for another microstep for my driver. It's a great challenge for me.
I thank again for these useful post and tutorial. Greatly appreciated!!!
Also, I thank everyone who contributed to writing this post.

Sorry for my english. I'm a little hard to write in English.

Dan

[H500]

I posted code for a 10 microstep version here:

http://www.cnczone.com/forums/open_s...p_bipolar.html