Interrupt driven.
When an edge generates an interrupt, ideally at the SAME TIME as the interrupt, BOTH A and B need to be read.
If the interrupt routine is reading A and or B AFTER the interrupt, it is possible the data may have already changed, so the wrong logic state is processed.
A good way to achieve this and get rid of the latency problem is to read the A and B bit on the same port and have each transition generate the the interrupt.
There are a lot of low end CPU's that can't do this. You can only tell it which pin will be the interrupt pin. We need more than one interrupt pin for proper operation.
Externally you can latch the state with a flip-flop to overcome the latency problem, but if you are going to spend money on extra parts to overcome the problem, you might just as well use a better (more expensive) CPU.
There are quadrature chips that do all the fancy timing stuff up to frequencies, that would require a Pentium, so the chip keep count and the CPU just examines the count and direction from the chip as required.
Bottom line. Can the CPU hack the pace. That's why the error signal is required. The CPU might be off in the weeds when it is needed.
Super X3. 3600rpm. Sheridan 6"x24" Lathe + more. Three ways to fix things: The right way, the other way, and maybe your way, which is possibly a faster wrong way.