[Mariss Freimanis]

lucas,

The dump circuit is unnecessary for recirculating mode standby. By definition the attack slope is steeper than the decay slope in this mode.

By the way H500's 06-12-2011, 09:43 AM post scope pictures show pronounced notches at the full-step locations (sin 0, 90, 180, etc.). This is due to an overly long reset pulse applied to the time-base counter. The reset pulse synchronizes the PWM to the step pulse frequency at the full-step rate. The purpose is to prevent beat frequencies between the step rate and the PWM frequency. An overly long reset duration introduces such artifacts.

Mariss

[lucas]

Thanks very much for all the info wich you provided to allow us hobbiests build a decent drive.

I have a machine running with CPLD drive's from your tutorial and PCB design using your recommendations on PCB layout, it's working fine.
Will try to see what difference the change on the DUMP signal makes.

4) Circle the projected beam on the wall with a pencil.

Writing on the wall was forbidden by my ex-wife and I do forbid it to my grandchild also... :devious:

Edit:

By the way H500's 06-12-2011, 09:43 AM post scope pictures show pronounced notches at the full-step locations (sin 0, 90, 180, etc.). This is due to an overly long reset pulse applied to the time-base counter. The reset pulse synchronizes the PWM to the step pulse frequency at the full-step rate. The purpose is to prevent beat frequencies between the step rate and the PWM frequency. An overly long reset duration introduces such artifacts.

I understand the synchronisation function between the step and PWM and I saw those notches also but seem to remember that there was a problem with the timebase counter, as far as I remember: The blanking period period doesn't start at the zero count. This didn't create problems with the original code but did when the code was modified for additional functions.
Have to check my notes but I think these notches were gone when I modified it.